True breakthroughs in computing don’t happen very often. When they do happen, what looks to the public like an out-of-the-blue announcement is actually the result of years or even decades of work. One company, Atomera, thinks it has developed a technology that could breathe new life into older process nodes and give customers a reason to move to newer, faster, processes — and there’s no reason its technology couldn’t be extended to boost newer chips as well.
Heading up this effort to extend Moore’s Law is Robert Mears, one of the inventors of Erbium Doped Fiber Amplifier (EDFA), a critical method of amplifying optical signals in fiber optic arrays without first converting those signals back into electricity. Atomera’s invention, if successful, could significantly impact the future of computing by offering real improvements to various manufacturers without requiring them to move to smaller process nodes.
One of the major differences between the various merchant foundries (GlobalFoundries, TSMC, Samsung, SMIC, UMC) and Intel is the process nodes they focus on. Intel has a fast-moving model that emphasizes moving to new nodes fairly quickly. It depends on the latest nodes for the bulk of its revenue, and it transitions older plants to newer nodes on a fairly regular basis. This model has taken a beating over the last few years, due to 14nm difficulties and the cancellation of 450mm wafers, but it’s still the basic way that Intel does business. TSMC and its merchant foundry competitors, however, tend to derive significant amounts of revenue from older hardware.
Keep in mind that this image is from Q1 2015, when 20nm was TSMC’s leading-edge node. What it shows is that 39% of TSMC’s revenue is derived from process nodes that the company debuted 10 or more years ago (the foundry’s 65nm semiconductor technology entered bulk production in 2006). If you include 40/45nm, which launched eight years ago, that figure rises to 54%. When merchant foundries refer to long versus short nodes today, what they’re referring to is a belief that certain nodes, like 28nm, will continue to be important for years to come.
There are multiple reasons why companies settle on a specific process node. The benefits of smaller processes tend to be specific to certain kinds of processors. We normally talk about chips built on conventional CMOS, but there are other types of manufacturing — analog, MEMS, and RF, to name a few. Even devices built on CMOS may not benefit from smaller nodes if, for example, they have a minimum pad size that a smaller node can’t shrink.
Alternatively, even a conventional CMOS design may not benefit from a die shrink if the current product doesn’t generate enough revenue to pay for the new design effort, or if the existing hardware is perceived as capable of meeting existing needs. IoT devices don’t necessarily need to be built on cutting-edge silicon nodes, particularly if the hardware in question is selling for $50 or less. These companies would benefit from better silicon technology, but they may not be able to justify moving to a new node to get it. That’s where Atomera’s new technology could come in handy.
Atomera’s Mears Silicon Technology (MST) works by inserting a layer of oxygen in between the silicon lattice as the latter forms. Call it “squeezed silicon” (that’s our name, not theirs) as opposed to the well-known “strained silicon” technique for improving silicon’s performance. Mears claims this lowers leakage and improves drive current, while simultaneously improving electron hole mobility. The total gains are estimated to be equivalent to a a half-node to full-node die shrink depending on the characteristics of the chip. The technology has been in development for over a decade, which is actually pretty normal in semiconductor manufacturing.
We’ve seen some evidence that semiconductor companies are looking for ways to improve existing nodes rather than simply chasing after new ones. TSMC rolled out a new 28nm offering, 28HPC+, starting in 2015 — more than three years after its 28nm node had entered volume production. The explicit goal of 28HPC+ was to offer significant improvements compared with TSMC’s older 28nm nodes (HP, LP, HPL, HPM) without requiring a die shrink. When Samsung began building 3D NAND, it announced that it would use an older 40nm process for at least the first few iterations of the product. The idea of improving nodes or taking advantage of older nodes isn’t something unique to Atomera.
We spoke to Atomera and confirmed that the company is ready to move beyond developing its technology and expects to announce some significant customers in the not-too-distant future. The company claims it can offer performance improvements equal to those that might be achieved by adopting III-V semiconductors or moving to sub-10nm nodes, at a fraction of the cost — but only if major fabs sign on. To date, none appear to have done so (EETimes notes that Atomera has won some legacy fabs, but doesn’t state which they are).
Right now, the semiconductor industry is trying to figure out which technologies will shape the future of next-generation nodes. If Atomera can demonstrate that its technology works on older products, it’ll have a much stronger opportunity to sell into major silicon designs in the future. If EUV doesn’t come online in the next few years, TSMC, GloFo, Samsung, and even Intel may all be hungry for a technology that lets them deliver a node worth of scaling without incurring massive additional design costs. Atomera still has to demonstrate that it represents a viable route forward — but design firms and companies across the silicon industry are looking for technology that would help them deliver new improvements without breaking the bank.
Now read: What is silicon, and why are computer chips made from it?